Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed components. For example, chip-to-chip data rates have traditionally been constrained by the bandwidth of input/output (I/O) circuitry in each component. However, process enhancements and innovations in I/O circuitry have forced designers to also consider the effects of the transmission channels between the chips on which data is sent.
At a basic level, data transmission between components within a single semiconductor device, or between two devices on a printed circuit board, may be represented by the system 10 shown in FIG. 1A. In FIG. 1A, a transmitter 12 (e.g., a microprocessor) sends data over a parallel bus 17 of channels 16 (e.g., copper traces on a printed circuit board or “on-chip” in a semiconductor device) to a receiver 14 (e.g., another processor or memory). When data is sent from an ideal transmitter 12 to a receiver 14 across ideal (lossless) channels 16, all of the energy in a transmitted pulse will be contained within a single time cell, which is often referred to as a unit interval (UI).
However, real transmitters and real transmission channels do not exhibit ideal characteristics. Due to a number of factors, including, for example, the limited conductivity of copper traces, the dielectric medium of the printed circuit board (PCB), and the discontinuities introduced by vias, the initially well-defined digital pulse will tend to spread or disperse as it passes through a particular channel 16. This is shown in FIG. 1B. As shown, a single pulse of data 105a is sent by the transmitter 12 during a given UI (e.g., UI3). However, because of the effect of the channel 16, this data pulse becomes spread 105b over multiple UIs at the receiver 14, i.e., some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI2 and UI4). This residual energy outside of the UI of interest may perturb a pulse otherwise occupying the neighboring UIs, in a phenomenon referred to as intersymbol interference (ISI).
Because of the potentially negative impact of ISI on the reliability of data transfer and detection at the receiver 14, it is important to simulate such data transfer in a computer system using simulation software. Simulation software allows the circuit designer to verify the operation and margins of a circuit design before incurring the expense of actually building and testing the circuit. Simulation is particularly important in the semiconductor industry, where it is generally very expensive to design and produce a given integrated circuit. Through the use of such simulations, design errors or risks are hopefully identified early in the design process, and resolved prior to fabrication.
A practical issue that confounds meaningful simulation is the reality of amplitude noise 106a and/or timing jitter 106b, as shown in FIG. 1B. Signals in any channel experience both random and deterministic amplitude noise and/or timing jitter. Random deviation, in the form of random Gaussian distributed amplitude noise and/or timing jitter stemming from thermal and shot noise, requires statistical quantification. Similarly, deterministic amplitude noise and/or timing jitter are linked to several sources including power supply noise, inter-channel crosstalk, impedance discontinuities, component variance, and at high frequencies the response of the channel, resulting in a variety of observable characteristics, from periodicity to uncorrelated-bounded randomness. To model amplitude noise 106a and/or timing jitter 106b correctly requires the ability to superimpose these effects into a simluatable signal in a way reflecting what occurs in the actual system.
The generation of realistic simulatable signals is exacerbated when the simulation involves not just transmission through a single channel, but rather requires simulation across multiple channels 16 in a parallel bus 17 (comprising, for example, 8, 16, or 32 parallel channels, etc.). Just as is it beneficial to simulate a statistically significant number of bits, it is also beneficial to simulate transmission of signals through a statistically significant number of channels 16 in the bus 17, if not all channels in the bus. This is because of the reality of cross-talk between channels 16 in the bus 17 and simultaneous switching noise (SSN) induced in the power supply distribution: i.e., one channel's signal and supply current draw may affect a signal on another channel.
Still another factor making simulation difficult is the reality that various types of data, prior to being transmitted, may require some type of encoding. For example, data bus inversion can work an inversion in some of the data on the channels in the bus prior to their transmission, which inversion is then undone or decoded at the receiver to recover the original data. See, e.g., U.S. patent application Ser. No. 11/873,779, filed Oct. 17, 2007, which is incorporated by reference in its entirety. One skilled in the art will recognize that other forms of encoding of signals in a parallel bus are also possible. In any event, understanding that the data will be encoded in an actual system further complicates the generation of simulatable signals.
With the following background in hand, it should be apparent that improved techniques are needed to quickly generate realistic simulation vectors to enable the simulation of the transmission of encoded data, which may or may not simultaneously exhibit amplitude noise and/or timing jitter, through a parallel bus. The disclosed technique provides such a solution.